The present invention relates to a semiconductor memory device making use of insulated gate field effect transistors (hereinafter called "IGFET's"), and more particularly to a structure of a memory capacitor section having a memory function in the semiconductor memory device.
The most widely used memory device employs the so-called "single-transistor type" memory cell which consists of a single IGFET and a capacitor coupled thereto. Memory cells are arranged in this memory in a matrix array and the gate of each IGFET is connected to a word line and one of its source and drain regions is connected to a digit line. The capacitor section is connected to the channel region of this IGFET either directly or via the other of the source and drain regions, and existence or non-existence of electric charge stored in this capacitor section serves as stored information. The capacitor is typically a MOS capacitor and the capacitance C.sub.s of this MOS capacitor is given by the formula of C.sub.s =.epsilon.S/t, where .epsilon. is a dielectric constant of an insulating film, S an electrode area of the capacitor section and t a thickness of the insulating film.
In recent years, in accordance with the progress of high circuit integration in semiconiuctor devices, microfining of circuit elements has been required. Even in micro-fining a memory device of single-transistor type, reduction of the value of the capacitance C.sub.s must be avoided to the utmost for the purpose of facilitating determination of stored information and maintaining a resistance against radioactive rays such as, for example, .alpha.-rays. Consequently, in the prior art increase of the capacitance C.sub.s was contemplated by thinning the thickness of the insulating film, but this approach also could not always be said to be a satisfactory method because of increase of a pin hole density, lowering of a withstand voltage or the like caused by thinning of the insulating film. On the other hand, in order to increase the area S for the purpose of contemplating increase of the capacitance C.sub.s, a method of forming a groove in the semiconductor substrate within a capacitor section area has been also proposed. However, since this method proposed in the prior art contemplated to form a groove always within each memory cell area, a plan area for forming this groove became necessary, and hence a high degree of circuit integration was not expected.